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general description the MAX9234/max9236/max9238 deserialize three lvds serial-data inputs into 21 single-ended lvcmos/lvttl outputs. a parallel-rate lvds clock received with the lvds data streams provides timing for deserialization. the outputs have a separate supply, allowing 1.8v to 5v output logic levels. all these devices are hot-swappable and allow ?n-the-fly?frequency programming. the MAX9234/max9236/max9238 feature dc balance, which allows isolation between a serializer and deseri- alizer using ac-coupling. each deserializer decodes data transmitted by one of the max9209/max9211/ max9213/max9215 serializers. the MAX9234 has a rising-edge output strobe. the max9236/max9238 have a falling-edge output strobe. the MAX9234/max9236/max9238 operate in dc- balanced mode only. the MAX9234/max9236 operate with a parallel input clock of 8mhz to 34mhz, while the max9238 operates from 16mhz to 66mhz. the transition time of the single- ended outputs is increased on the low-frequency version parts (MAX9234/max9236) for reduced emi. the lvds inputs meet iso 10605 esd specification, ?5kv for air- gap discharge and ?kv contact discharge. the MAX9234/max9236/max9238 are available in 48-pin tssop packages and operate over the -40? to +85? temperature range. applications automotive navigation systems automotive dvd entertainment systems digital copiers laser printers features ? dc balance allows ac-coupling for wider input common-mode voltage range ? on-the-fly frequency programming ? operating frequency range 8mhz to 34mhz (MAX9234/max9236) 16mhz to 66mhz (max9238) ? falling-edge output strobe (max9236/max9238) ? slower output transitions for reduced emi (MAX9234/max9236) ? high-impedance outputs when pwrdwn is low allow output busing ? 5v-tolerant pwrdwn input ? pll requires no external components ? up to 1.386gbps throughput ? separate output supply pins allow interface to 1.8v, 2.5v, 3.3v, and 5v logic ? lvds inputs meet iso 10605 esd requirements ? lvds inputs conform to ansi tia/eia-644 lvds standard ? low-profile, 48-lead tssop package ? +3.3v main power supply ? -40? to +85? operating temperature range MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers ________________________________________________________________ maxim integrated products 1 ordering information 19-3641; rev 1; 10/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. functional diagram and pin configuration appear at end of data sheet. part temp range pin- package pkg code MAX9234 eum -40? to +85? 48 tssop u48-1 max9236 eum -40? to +85? 48 tssop u48-1 max9238 eum -40? to +85? 48 tssop u48-1
MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +3.6v, v cco = +3.0v to +5.5v, pwrdwn = high, differential input voltage ? v id ? = 0.05v to 1.2v, input common- mode voltage v cm = ? v id /2 ? to 2.4v - ? v id /2 ? , t a = -40? to +85?, unless otherwise noted. typical values are at v cc = v cco = +3.3v, ? v id ? = 0.2v, v cm = 1.25v, t a = +25?.) (notes 1, 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ...........................................................-0.5v to +4.0v v cco to gnd.........................................................-0.5v to +6.0v rxin_, rxclk in_ to gnd ....................................-0.5v to +4.0v pwrdwn to gnd....................................................-0.5v to 6.0v rxout_, rxclk out to gnd ................-0.5v to (v cco + 0.5v) continuous power dissipation (t a = +70?) 48-pin tssop (derate 16mw/? above +70?) ....... 1282mw storage temperature range .............................-65? to +150? junction temperature ......................................................+150? esd protection human body model (r d = 1.5k , c s = 100pf) all pins to gnd ..................................??kv iec 61000-4-2 (r d = 330 , cs = 150pf) contact discharge (rxin_, rxclk in_) to gnd .........?kv air-gap discharge (rxin_, rxclk in_) to gnd .......?5kv iso 10605 (r d = 2k , c s = 330pf) contact discharge (rxin_, rxclk in_) to gnd ........?kv air discharge (rxin_, rxclk in_) to gnd ...............?5kv lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units single-ended input ( pwrdwn ) high-level input voltage v ih 2.0 5.5 v low-level input voltage v il -0.3 +0.8 v input current i in v in = high or low -70 +70 ? input clamp voltage v cl i cl = -18ma -1.5 v single-ended outputs (rxout_, rxclk out) i oh = -100? v cco - 0.1 rxclk out v cco - 0.25 MAX9234/ max9236 rxout_ v cco - 0.40 high-level output voltage v oh i oh = -2ma max9238 v cco - 0.25 v i ol = 100? 0.1 rxclk out 0.2 MAX9234/ max9236 rxout_ 0.26 low-level output voltage v ol i ol = 2ma max9238 0.2 v high-impedance output current i oz pwrdwn = low, v out_ = -0.3v to v cco + 0.3v -20 +20 ? rxclk out -10 -40 MAX9234/ max9236 rxout_ -5 -20 v cco = 3.0v to 3.6v, v out = 0 max9238 -10 -40 rxclk out -28 -75 MAX9234/ max9236 rxout_ -14 -37 output short-circuit current (note: short one output at a time.) i os v cco = 4.5v to 5.5v, v out = 0 max9238 -28 -75 ma
MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc = +3.0v to +3.6v, v cco = +3.0v to +5.5v, pwrdwn = high, differential input voltage ? v id ? = 0.05v to 1.2v, input common- mode voltage v cm = ? v id /2 ? to 2.4v - ? v id /2 ? , t a = -40? to +85?, unless otherwise noted. typical values are at v cc = v cco = +3.3v, ? v id ? = 0.2v, v cm = 1.25v, t a = +25?.) (notes 1, 2) parameter symbol conditions min typ max units lvds inputs differential input-high threshold v th 50 mv differential input-low threshold v tl -50 mv input current i in+ , i in- pwrdwn = high or low -25 +25 ? power-off input current i ino+ , i ino- v cc = v cco = 0 or open, pwrdwn = 0 or open -40 +40 ? pwrdwn = high or low (figure 1) input resistor 1 r in1 v cc = v cco = 0 or open (figure 1) 42 78 k power supply 8mhz 42 16mhz 57 MAX9234/ max9236 34mhz 98 16mhz 63 34mhz 106 worst-case supply current i ccw c l = 8pf, worst-case pattern; v cc = v cco = 3.0v to 3.6v, figure 2 max9238 66mhz 177 ma power-down supply current i ccz pwrdwn = low 50 ?
MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers 4 _______________________________________________________________________________________ note 1: current into a pin is defined as positive. current out of a pin is defined as negative. all voltages are referenced to ground except v th and v tl . note 2: maximum and minimum limits overtemperature are guaranteed by design and characterization. devices are production tested at t a = +25?. note 3: ac parameters are guaranteed by design and characterization, and are not production tested. limits are set at ? sigma. note 4: c l includes probe and test jig capacitance. note 5: rcip is the period of rxclk in. rcop is the period of rxclk out. rcip = rcop. note 6: rskm measured with 150ps cycle-to-cycle jitter on rxclk in. ac electrical characteristics (v cc = v cco = +3.0v to +3.6v, 100mv p-p at 200khz supply noise, c l = 8pf, pwrdwn = high, differential input voltage ? v id ? = 0.1v to 1.2v, input common mode voltage v cm = ? v id /2 ? to 2.4v - ? v id /2 ? , t a = -40? to +85?, unless otherwise noted. typical values are at v cc = v cco = +3.3v, ? v id ? = 0.2v, v cm = 1.25v, t a = +25?.) (notes 3, 4, 5) parameter symbol conditions min typ max units rxout 3.52 5.04 6.24 MAX9234/ max9236 rxclk out 2.2 3.15 3.9 output rise time clht 0.1v cco to 0.9v cco , figure 3 max9238 2.2 3.15 3.9 ns rxout 1.95 3.18 4.35 MAX9234/ max9236 rxclk out 1.3 2.12 2.9 output fall time chlt 0.9v cco to 0.1v cco , figure 3 max9238 1.3 2.12 2.9 ns 8mhz 6600 7044 16mhz 2560 3137 34mhz 900 1327 rxin skew margin rskm figure 4 (note 6) max9238 66mhz 330 685 ps rxclk out high time rcoh figures 5a, 5b 0.35 x rcop ns rxclk out low time rcol figures 5a, 5b 0.35 x rcop ns rxout setup to rxclk out rsrc figures 5a, 5b 0.30 x rcop ns rxout hold from rxclk out rhrc figures 5a, 5b 0.45 x rcop ns rxclk in to rxclk out delay rccd figures 6a, 6b 4.9 6.17 8.1 ns deserializer phase-locked loop set rplls figure 7 32800 x rcip ns deserializer power-down delay rpdd figure 8 100 ns
MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers _______________________________________________________________________________________ 5 MAX9234/max9236 worst-case pattern and prbs supply current vs. frequency MAX9234/6/8 toc01 frequency (mhz) supply current (ma) 30 25 20 15 10 40 30 50 60 70 80 90 100 540 35 worst case 2 7 - 1 prbs max9238 worst-case pattern and prbs supply current vs. frequency MAX9234/6/8 toc02 frequency (mhz) supply current (ma) 60 50 40 30 20 60 40 80 100 120 140 160 180 10 70 worst case 2 7 - 1 prbs MAX9234/max9236 rxout transition time vs. output supply voltage (v cco ) MAX9234/6/8 toc03 output supply voltage (v) output transition time (ns) 4.5 4.0 3.5 3.0 1 2 3 4 5 6 7 2.5 5.0 clht chlt max9238 rxout transition time vs. output supply voltage (v cco ) MAX9234/6/8 toc04 output supply voltage (v) output transition time (ns) 4.5 4.0 3.5 3.0 0 1 2 3 4 5 2.5 5.0 clht chlt typical operating characteristics (v cc = v cco = +3.3v, c l = 8pf, pwrdwn = high, differential input voltage ? v id ? = 0.2v, input common-mode voltage v cm = 1.2v, t a = +25?, unless otherwise noted.)
MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers 6 _______________________________________________________________________________________ pin description pin name function 1, 2, 4, 5, 45, 46, 47 rxout14?xout20 channel 2 single-ended outputs 3, 25, 32, 38, 44 gnd ground 6 n.c. no connection 7, 13, 18 lvds gnd lvds ground 8 rxin0- inverting channel 0 lvds serial-data input 9 rxin0+ noninverting channel 0 lvds serial-data input 10 rxin1- inverting channel 1 lvds serial-data input 11 rxin1+ noninverting channel 1 lvds serial-data input 12 lvds v cc lvds supply voltage. bypass to lvds gnd with 0.1? and 0.001? capacitors in parallel as close to lvds v cc as possible, with the smallest value capacitor closest to the supply pin. 14 rxin2- inverting channel 2 lvds serial-data input 15 rxin2+ noninverting channel 2 lvds serial-data input 16 rxclk in- inverting lvds parallel rate clock input 17 rxclk in+ noninverting lvds parallel rate clock input 19, 21 pll gnd pll ground 20 pll v cc pll supply voltage. bypass to pll gnd with 0.1? and 0.001? capacitors in parallel as close to pll v cc as possible, with the smallest value capacitor closest to the supply pin. 22 pwrdwn 5v tolerant lvttl/lvcmos power-down input. internally pulled down to gnd. outputs are high impedance when pwrdwn = low or open. 23 rxclk out parallel rate clock single-ended output. the MAX9234 has a rising-edge strobe. the max9236/max9238 have a falling-edge strobe. 24, 26, 27, 29, 30, 31, 33 rxout0?xout6 channel 0 single-ended outputs 28, 36, 48 v cco output supply voltage. bypass to gnd with 0.1? and 0.001? capacitors in parallel as close to v cco as possible, with the smallest value capacitor closest to the supply pin. 34, 35, 37, 39, 40, 41, 43 rxout7?xout13 channel 1 single-ended outputs 42 v cc digital supply voltage. bypass to gnd with 0.1? and 0.001? capacitors in parallel as close to v cc as possible, with the smallest value capacitor closest to the supply pin.
MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers _______________________________________________________________________________________ 7 detailed description the MAX9234/max9236 operate at a parallel clock fre- quency of 8mhz to 34mhz. the max9238 operates at a parallel clock frequency of 16mhz to 66mhz. the tran- sition times of the single-ended outputs are increased on the MAX9234/max9236 for reduced emi. dc balance data coding by the max9209/max9211/max9213/ max9215 serializers (which are companion devices to the MAX9234/max9236/max9238 deserializers) limits the imbalance of ones and zeros transmitted on each channel. if +1 is assigned to each binary 1 transmitted and -1 is assigned to each binary 0 transmitted, the varia- tion in the running sum of assigned values is called the digital sum variation (dsv). the maximum dsv for the data channels is 10. at most, 10 more zeros than ones, or 10 more ones than zeros, are transmitted. the maxi- mum dsv for the clock channel is five. limiting the dsv and choosing the correct coupling capacitors maintains differential signal amplitude and reduces jitter due to droop on ac-coupled links. to obtain dc balance on the data channels, the serial- izer parallel data is inverted or not inverted, depending on the sign of the digital sum at the word boundary. two complementary bits are appended to each group of 7 parallel input data bits to indicate to the MAX9234/ max9236/max9238 deserializers whether the data bits are inverted (see figure 9). the deserializer restores the original state of the parallel data. the lvds clock signal alternates duty cycles of 4/9 and 5/9, which maintain dc balance. ac-coupling benefits bit errors experienced with dc-coupling can be elimi- nated by increasing the receiver common-mode voltage range by ac-coupling. ac-coupling increases the com- mon-mode voltage range of an lvds receiver to nearly the voltage rating of the capacitor. the typical lvds dri- ver output is 350mv centered on an offset voltage of 1.25v, making single-ended output voltages of 1.425v and 1.075v. an lvds receiver accepts signals from 0 to 2.4v, allowing approximately 1v common-mode differ- ence between the driver and receiver on a dc-coupled link (2.4v - 1.425v = 0.975v and 1.075v - 0v = 1.075v). common-mode voltage differences may be due to ground potential variation or common-mode noise. if there is more than 1v of difference, the receiver is not guaranteed to read the input signal correctly and may cause bit errors. ac-coupling filters low-frequency ground shifts and common-mode noise and passes high-frequency data. a common-mode voltage differ- ence up to the voltage rating of the coupling capacitor (minus half the differential swing) is tolerated. dc-bal- anced coding of the data is required to maintain the dif- ferential signal amplitude and limit jitter on an ac-coupled link. a capacitor in series with each output of the lvds driver is sufficient for ac-coupling. however, two capacitors?ne at the serializer output and one at the deserializer input?rovide protection in case either end of the cable is shorted to a high voltage. rin1 rxin_ + or rxclk in+ rxin_ - or rxclk in- rin1 1.2v figure 1. lvds input circuit rcip rxclk out odd rxout even rxout rising-edge strobe shown. figure 2. worst-case test pattern table 1. part equivalent table part equivalent with dcb/nc = high or open operating frequency (mhz) output strobe MAX9234 max9210 8 to 34 rising edge max9236 max9220 8 to 34 falling edge max9238 max9222 16 to 66 falling edge
MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers 8 _______________________________________________________________________________________ ideal min max internal strobe ideal rskm rskm ideal serial bit time 1.3v 1.1v figure 4. lvds receiver input skew margin rxout_ rxclk out rcip rcoh rcol 2.0v 0.8v 2.0v 0.8v 2.0v 2.0v 2.0v 0.8v 0.8v rhrc rsrc figure 5a. MAX9234 output setup/hold and high/low times rxout_ rxclk out rcip rcoh rcol 2.0v 0.8v 2.0v 0.8v 2.0v 2.0v 0.8v 0.8v 0.8v rhrc rsrc figure 5b. max9236/max9238 output setup/hold and high/low times v id = 0 1.5v rccd rxclk in rxclk out figure 6a. MAX9234 clock-in to clock-out delay rxclk in rxclk out + - rccd 1.5v v id = 0 figure 6b. max9236/max9238 clock-in to clock-out delay 90% 90% 10% 10% chlt clht rxout_ or rxclk out rxout_ or rxclk out 8pf figure 3. output load and transition times pwrdwn v cc rxclk in rxclk out 3v 2v rplls high-z figure 7. phase-locked loop set time
MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers _______________________________________________________________________________________ 9 MAX9234/max9236/max9238 vs. max9210/max9220/max9222 the MAX9234/max9236/max9238 operate in dc-bal- ance mode only. pinouts are the same as the max9210/max9220/max9222 except that pin 6 on the MAX9234/max9236/max9238 is no connect (n.c.). dc balance allows ac-coupling with series capacitors. the MAX9234/max9236/max9238 are hot-swappable and the input frequency can be changed on the fly, but oth- erwise the specifications and functionality are the same as the max9210/max9220/max9222 operating in dc- balance mode. see table 1. applications information selection of ac-coupling capacitors voltage droop and the dsv of transmitted symbols cause signal transitions to start from different voltage levels. because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the lvds receiver termination resistor (r t ), the lvds driver output resistor (r o ), and the series ac-coupling capac- itors (c). the rc time constant for two equal-value series capacitors is (c x (r t + r o )) / 2 (figure 10). the rc time constant for four equal-value series capacitors is (c x (r t + r o )) / 4 (figure 11). r t is required to match the transmission line imped- ance (usually 100 ) and r o is determined by the lvds driver design (the minimum differential output resis- tance of 78 for the max9209/max9211/max9213/ max9215 serializers is used in the following example). this leaves the capacitor selection to change the sys- tem time constant. txin_, dca_, and dcb_ are data from the serializer. dca0 dcb1 dca1 dcb2 dca2 cycle n + 1 cycle n cycle n - 1 txin2 txin6 txin3 txin4 txin5 txin9 txin13 txin10 txin11 txin12 txin2 txin3 txin4 dca0 txin5 txin6 dcb0 txin9 txin10 txin11 dca1 txin12 txin13 dcb1 txin16 txin17 txin18 dca2 txin19 txin20 dcb2 txin0 txin1 txin7 txin8 txin14 txin15 txin16 txin20 txin17 txin18 txin19 dcb0 rxclk in rxin1 rxin0 rxin2 txin1 txin8 txin15 txin0 txin7 txin14 + - figure 9. deserializer serial input 0.8v pwrdwn rxclk in rxout_ rxclk out rpdd high-z figure 8. power-down delay
MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers 10 ______________________________________________________________________________________ (7 + 2):1 1:(9 - 2) 7 7 100 (7 + 2):1 1:(9 - 2) 7 7 100 (7 + 2):1 1:(9 - 2) 7 7 100 pll pll 100 max9209 max9211 max9213 max9215 MAX9234 max9236 max9238 txout txclk out rxin rxclk in 21:3 serializer 3:21 deserializer pwrdwn rxclk out rxout pwrdwn txclk in txin high-frequency, ceramic surface-mount capacitors can also be placed at the serializer instead of the deserializer. figure 10. two capacitors per link, ac-coupled (7 + 2):1 1:(9 - 2) 7 7 100 (7 + 2):1 1:(9 - 2) 7 7 100 (7 + 2):1 1:(9 - 2) 7 7 100 pll pll 100 max9209 max9211 max9213 max9215 MAX9234 max9236 max9238 txout txclk out rxin rxclk in 21:3 serializer 3:21 deserializer pwrdwn rxclk out rxout pwrdwn txclk in txin high-frequency ceramic surface-mount capacitors figure 11. four capacitors per link, ac-coupled
MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers ______________________________________________________________________________________ 11 in the following example, the capacitor value for a droop of 2% is calculated. jitter due to this droop is then calculated assuming a 1ns transition time: c = - (2 x t b x dsv) / (ln (1 - d) x (r t + r o )) (eq 1) where: c = ac-coupling capacitor (f). t b = bit time (s). dsv = digital sum variation (integer). ln = natural log. d = droop (% of signal amplitude). r t = termination resistor ( ). r o = output resistance ( ). equation 1 is for two series capacitors (figure 10). the bit time (t b ) is the period of the parallel clock divided by 9. the dsv is 10. see equation 3 for four series capaci- tors (figure 11). the capacitor for 2% maximum droop at 8mhz parallel rate clock is: c = - (2 x t b x dsv) / (ln (1 - d) x (r t + r o )) c = - (2 x 13.9ns x 10) / (ln (1 - 0.02) x (100 + 78 )) c = 0.0773? jitter due to droop is proportional to the droop and transition time: t j = t t x d (eq 2) where: t j = jitter (s). t t = transition time (s) (0 to 100%). d = droop (% of signal amplitude). jitter due to 2% droop and assumed 1ns transition time is: t j = 1ns x 0.02 t j = 20ps the transition time in a real system depends on the fre- quency response of the cable driven by the serializer. the capacitor value decreases for a higher frequency parallel clock and for higher levels of droop and jitter. use high-frequency, surface-mount ceramic capacitors. equation 1 altered for four series capacitors (figure 11) is: c = - (4 x t b x dsv) / (ln (1 - d) x (r t + r o )) (eq 3) input bias and frequency detection the inverting and noninverting lvds inputs are internally connected to +1.2v through 42k (min) to provide bias- ing for ac-coupling (figure 1). a frequency-detection circuit on the clock input detects when the input is not switching, or is switching at low frequency. in this case, all outputs are driven low. to prevent switching due to noise when the clock input is not driven, bias the clock input to differential +15mv by connecting a 10k ?% pullup resistor between the noninverting input and v cc , and a 10k ?% pulldown resistor between the invert- ing input and ground. these bias resistors, along with the 100 ?% tolerance termination resistor, provide +15mv of differential input. unused lvds data inputs at each unused lvds data input, pull the inverting input up to v cc using a 10k resistor, and pull the noninverting input down to ground using a 10k resistor. do not con- nect a termination resistor. the pullup and pulldown resis- tors drive the corresponding outputs low and prevent switching due to noise. pwrdwn driving pwrdwn low puts the outputs in high imped- ance, stops the pll, and reduces supply current to 50? or less. driving pwrdwn high drives the outputs low until the pll locks. the outputs of two deserializers can be bused to form a 2:1 mux with the outputs con- trolled by pwrdwn . wait 100ns between disabling one deserializer (driving pwrdwn low) and enabling the second one (driving pwrdwn high) to avoid con- tention of the bused outputs. input clock and pll lock time there is no required timing sequence for the applica- tion or reapplication of the parallel rate clock (rxclk in) relative to pwrdwn , or to a power-supply ramp for proper pll lock. the pll lock time is set by an internal counter. the maximum time to lock is 32,800 clock periods. power and clock should be stable to meet the lock-time specification. when the pll is locking, the outputs are low. power-supply bypassing there are separate on-chip power domains for digital circuits, outputs, pll, and lvds inputs. bypass each v cc , v cco , pll v cc , and lvds v cc pin with high-fre- quency, surface-mount ceramic 0.1? and 0.001? capacitors in parallel as close to the device as possi- ble, with the smallest value capacitor closest to the supply pin. cables and connectors interconnect for lvds typically has a differential imped- ance of 100 . use cables and connectors that have matched differential impedance to minimize impedance discontinuities. twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less emi due to magnetic field cancel- ing effects. balanced cables pick up noise as common mode, which is rejected by the lvds receiver.
MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers 12 ______________________________________________________________________________________ board layout keep the lvttl/lvcmos outputs and lvds input sig- nals separated to prevent crosstalk. a four-layer pc board with separate layers for power, ground, lvds inputs, and digital signals is recommended. esd protection the MAX9234/max9236/max9238 esd tolerance is rated for iec 61000-4-2 human body model and iso 10605 standards. iec 61000-4-2 and iso 10605 specifiy esd tolerance for electronic systems. the human body model discharge components are c s = 100pf and r d = 1.5k (figure 12). for the human body model, all pins are rated for ?kv contact discharge. the iso 10605 dis- charge components are c s = 330pf and r d = 2k (figure 13). for iso 10605, the lvds outputs are rated for ?kv contact and ?5kv air discharge. the iec 61000-4-2 discharge components are c s = 150pf and r d = 330 (figure 14). for iec 61000-4-2, the lvds inputs are rated for ?kv contact discharge and ?5kv air-gap discharge. 5v tolerant input pwrdwn is 5v tolerant and is internally pulled down to gnd. skew margin (rskm) skew margin (rskm) is the time allowed for degrada- tion of the serial data sampling setup and hold times by sources other than the deserializer. the deserializer sampling uncertainty is accounted for and does not need to be subtracted from rskm. the main outside contributors of jitter and skew that subtract from rskm are interconnect intersymbol interference, serializer pulse position uncertainty, and pair-to-pair path skew. v cco output supply and power dissipation the outputs have a separate supply (v cco ) for interfacing to systems with 1.8v to 5v nominal input-logic levels. the dc electrical characteristics table gives the maximum supply current for v cco = 3.6v with 8pf load at several switching frequencies with all outputs switching in the worst-case switching pattern. the approximate incremen- tal supply current for v cco other than 3.6v with the same 8pf load and worst-case pattern can be calculated using: i i = c t v i 0.5f c x 21 (data outputs) + c t v i f c x 1 (clock output) where: i i = incremental supply current. c t = total internal (c int ) and external (c l ) load capaci- tance. v i = incremental supply voltage. f c = output clock-switching frequency. the incremental current is added to (for v cco > 3.6v) or subtracted from (for v cco < 3.6v) the dc electrical characteristics table maximum supply current. the internal output buffer capacitance is c int = 6pf. the worst-case pattern-switching frequency of the data out- puts is half the switching frequency of the output clock. in the following example, the incremental supply current is calculated for v cco = 5.5v, f c = 34mhz, and c l = 8pf: v i = 5.5v - 3.6v = 1.9v c t = c int + c l = 6pf + 8pf = 14pf figure 13. iso 10605 contact discharge esd test circuit figure 12. human body esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r1 1m r2 1.5k c s 100pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r1 50 to 100 r2 2k c s 330pf figure 14. iec 61000-4-2 contact discharge esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 50 to 100 r d 330 c s 150pf
MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers ______________________________________________________________________________________ 13 where: i i = c t v i 0.5f c x 21 (data outputs) + c t v i f c x 1 (clock output). i i = (14pf x 1.9v x 0.5 x 34mhz x 21) + (14pf x 1.9v x 34mhz). i i = 9.5ma + 0.9ma = 10.4ma. the maximum supply current in dc-balanced mode for v cc = v cco = 3.6v at f c = 34mhz is 106ma (from the dc electrical characteristics table). add 10.4ma to get the total approximate maximum supply current at v cco = 5.5v and v cc = 3.6v. if the output supply voltage is less than v cco = 3.6v, the reduced supply current can be calculated using the same formula and method. at high switching frequency, high supply voltage, and high capacitive loading, power dissipation can exceed the package power-dissipation rating. do not exceed the maximum package power-dissipation rating. see the absolute maximum ratings for maximum package power-dissipation capacity and temperature derating. rising- or falling-edge output strobe the MAX9234 has a rising-edge output strobe, which latches the parallel output data into the next chip on the rising edge of rxclk out. the max9236/max9238 have a falling-edge output strobe, which latches the parallel output data into the next chip on the falling edge of rxclk out. the deserializer output strobe polarity does not need to match the serializer input strobe polarity. a deserializer with rising- or falling- edge output strobe can be driven by a serializer with a rising-edge input strobe. rxin0+ lvds data receiver 0 rxin0- strobe data channel 0 rxout0? serial-to- parallel converter rxin1+ lvds data receiver 1 rxin1- strobe data channel 1 rxout7?3 serial-to- parallel converter rxin2+ lvds data receiver 2 rxin2- strobe data channel 2 rxout14?0 serial-to- parallel converter rxclk in+ lvds clock receiver rxclk in- 9x pll rxclk out reference clock generator pwrdwn functional diagram 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 v cco rxout16 rxout15 rxout14 rxout19 gnd rxout18 rxout17 top view MAX9234 max9236 max9238 gnd rxout13 v cc rxout12 rxin0- lvds gnd n.c. rxout20 rxout11 rxout10 rxin1- rxin0+ 38 37 36 35 34 33 32 31 30 29 gnd rxout9 v cco rxout8 rxout7 rxout6 gnd rxout5 rxout4 rxout3 11 12 13 14 15 16 17 18 19 rxin2- lvds gnd lvds v cc rxin1+ lvds gnd rxclk in+ rxclk in- rxin2+ pll v cc pll gnd 20 21 pwrdwn pll gnd 22 28 27 v cco rxout2 tssop 23 rxout0 rxclk out 24 26 25 rxout1 gnd pin configuration chip information MAX9234 transistor count: 14,104 max9236 transistor count: 14,104 max9238 transistor count: 14,104 process: cmos
MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers 14 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 48l tssop.eps notes: 1. dimensions d & e are reference datums and do not include mold flash. 2. mold flash or protrusions not to exceed 0.15mm on d side, and 0.25mm on e side. 3. controlling dimension: millimeters. 4. this part is compliant with jedec specification mo-153, variations, ed (48l), ee (56l). 5. "n" refers to number of leads. 6. the lead tips must lie within a specified zone. this tolerance zone is defined by two parallel planes. one plane is the seating plane, datum (-c-), the other plane is at the specified distance from (-c-) in the direction indicated. 7. marking is for package orientation reference only. 8. number of leads shown are for reference only. section c-c detail a n side view top view c l 1 h e e d b a a2 a1 bottom view c 0.25 ( ) b1 b c1 base metal c end view seating plane see detail a parting line with plating l package outline, 21-0155 1 1 c 48 & 56l tssop, 6.1mm body aaa 23 a marking
MAX9234/max9236/max9238 hot-swappable, 21-bit, dc-balanced lvds deserializers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/05 initial release 1 10/07 added iec 61000-4-2 esd performance; various style changes 1, 2, 4, 5, 6, 12

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